Digital signal lines are used to transmit digital signals between a transmitter and a receiver. The signal lines may be “on-chip” signal lines that connect various subsystems on a single integrated circuit chip. For example, on-chip signal lines may connect a memory subsystem with a processor or host subsystem on a single integrated circuit chip. The on-chip digital signals may be, for example, data signals from a memory subsystem, often referred to as “DQ” signals. Alternatively, the signal lines may be “off-chip” signal lines, wherein output drivers drive a digital signal off an integrated circuit chip over a signal line that connects a given chip with another chip, another level of packaging or with an external system.
As the clock speeds of digital signals continue to increase, for example approaching 1 GHz or more, skew between/among adjacent signal lines may become increasingly problematic. In particular, as is well known to those having skill in the art, skew may be introduced among adjacent signal lines, so that signals that are transmitted synchronously over the signal lines may arrive at different times. Skew may be defined as the time difference or delay difference of a signal that passes through two transmission paths having different time delays.
As is well known to those having skill in the art, there are many potential causes of skew. For example, the different signal lines may have different physical lengths. This line length difference may cause skew. Moreover, the different signal lines may have different capacitances (actual and/or parasitic), which may also cause skew. The signals being transmitted over different signal lines may also pass through different numbers of gates, which may also cause skew. Skew also may be caused when output drivers have different output impedance and/or when different types of gates are used. There may also be other causes of skew. As the transmission speeds of digital signals continue to increase, skew may become more problematic. In particular, skew may limit the ultimate speed of the circuit and/or may reduce the operating margins thereof. Accordingly, techniques have been developed to reduce skew.
For example, it is known to add additional delay on the short delay path, to thereby equalize delay with a longer delay path. Unfortunately, this may increase the complexity of the transmitting or receiving circuit, and may also be difficult to implement when the time delay difference is variable. Various Delay Lock Loop (DLL) and/or Phase Lock Loop (PLL) techniques have also been used to lock in one signal to another. Unfortunately, these techniques may also add to the circuit complexity and a DLL/PLL may introduce its own delay due to locking time of the DLL/PLL.
Another technique for compensating for skew is described in U.S. Patent Application Publication US 2001/0055344 A1 entitled “Signal Transmission Circuit And Method For Equalizing Disparate Delay Times Dynamically, And Data Latch Circuit Of Semiconductor Device Implementing The Same”, assigned to the assignee of the present invention, the disclosure of which is hereby incorporated by reference in its entirety as if set forth fully herein. As disclosed in the Abstract of this U.S. patent application publication, a signal transmission circuit and a method equalize differential delay characteristics of two signal transmission lines. A controllable delay unit is connected serially to the second line, so as to compensate by adding its internal delay. An auxiliary signal transmission line replicates the second transmission line, while it processes the input signal of the first. A controlling unit compares the output signal of the first transmission line and the auxiliary signal transmission line, and adjusts dynamically the internal delay of the controllable delay unit, to attain continuous synchronization. A data latch circuit synchronizes the delays of data paths by having one controllable delay units in each of the data paths.